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Freescale Semiconductor Advance Information
Document Number: MPC17533 Rev. 3.0, 7/2006
0.7 A 6.8 V Dual H-Bridge Motor Driver
The 17533 is a monolithic dual H-Bridge power IC ideal for portable electronic applications containing bipolar stepper motors and/or brush DC-motors (e.g., cameras and disk drive head positioners). The 17533 operates from 2.0 V to 6.8 V, with independent control of each H-Bridge via parallel MCU interface (3.0 V- and 5.0 V-compatible logic). The device features built-in shoot-through current protection and an undervoltage shutdown function. The 17533 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). The 17533 has a low total RDS(ON) of 1.2 (max @ 25C). The 17533's low output resistance and high slew rates provide efficient drive for many types of micromotors. Features * Low Total RDS(ON) 0.8 (Typ), 1.2 (Max) @ 25C * Output Current 0.7 A (DC), 1.4 A (Peak) * Shoot-Through Current Protection Circuit * 3.0 V/ 5.0 V CMOS-Compatible Inputs * PWM Control Input Frequency up to 200 kHz * Built-In 2-Channel H-Bridge Driver * Low Power Consumption * Undervoltage Detection and Shutdown Circuit * Pb-Free Packaging Designated by Suffix Code EV
17533
H-BRIDGE MOTOR DRIVER
EV SUFFIX (Pb-FREE) 98ASA10614D 16-PIN VMFP
ORDERING INFORMATION
Device MPC17533EV/EL Temperature Range (TA) -20C to 65C Package 16 VMFP
5.0 V 13 V 17533 VDD VG
5.0 V VM OUT1A OUT1B
MCU
IN1A IN1B IN2A IN2B OE
OUT2A OUT2B
S
N
Bipolar Step Motor
GND
Figure 1. 17533 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2006. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VG
LowVoltage Shutdown VDD VM1
IN1A
H-Bridge 1
OUT1A OUT1B
IN1B VDD PGND1
OE
Control Logic
Level Shifter Predriver
VM2
IN2A OUT2A
H-Bridge 2
OUT2B IN2B
LGND
PGND2
Figure 2. 17533 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
OUT1A VM1 IN1A IN1B VDD OE LGND OUT1B
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
PGND2 OUT2A IN2A IN2B VG VM2 OUT2B PGND1
Figure 3. 17533 Pin Connections Table 1. PIN Function Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name OUT1A VM1 IN1A IN1B VDD OE LGND OUT1B PGND1 OUT2B VM2 VG IN2B IN2A OUT2A PGND2 Formal Name H-Bridge Output 1A Motor Drive Power Supply 1 Logic Input Control 1A Logic Input Control 1B Logic Supply Output Enable Logic Ground H-Bridge Output 1B Power Ground 1 H-Bridge Output 2B Motor Drive Power Supply 2 Output A of H-Bridge channel 1. Positive power source connection for H-Bridge 1 (Motor Drive Power Supply). Logic input control of OUT1A (refer to Table 5, Truth Table, page 7). Logic input control of OUT1B (refer to Table 5, Truth Table, page 7). Control circuit power supply pin. Logic output Enable control of H-Bridges (Low = True). Low-current logic signal ground. Output B of H-Bridge channel 1. High-current power ground 1. Output B of H-Bridge channel 2. Positive power source connection for H-Bridge 2 (Motor Drive Power Supply). Definition
Gate Driver Circuit Voltage Input Input pin for the gate drive voltage. Logic Input Control 2B Logic Input Control 2A H-Bridge Output 2A Power Ground 2 Logic input control of OUT2B (refer to Table 5, Truth Table, page 7). Logic input control of OUT2A (refer to Table 5, Truth Table, page 7). Output A of H-Bridge channel 2. High-current power ground 2.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent damage to the device.
Rating Motor Supply Voltage Gate Driver Circuit Power Supply Voltage Logic Supply Voltage Signal Input Voltage Driver Output Current Continuous Peak (1) ESD Voltage
(2)
Symbol VM VG VDD VIN IO IOPK
Value -0.5 to 8.0 -0.5 to 14 -0.5 to 7.0 -0.5 to VDD + 0.5 0.7 1.4
Unit V V V V A
V VESD1 VESD2 TJ TA TSTG RJA PD
(5)
Human Body Model Machine Model Operating Junction Temperature Operating Ambient Temperature Storage Temperature Range Thermal Resistance Power Dissipation
(3)
1500 200 -55 to 150 -20 to 65 -55 to 150 150 830 260 C C C C/W mW C
(4)
Pin Soldering Temperature
TSOLDER
Notes 1. TA = 25C. 10 ms pulse at 200 ms intervals. 2. 3. 4. 5. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). Mounted on 37 mm x 50 mm x 1.6 mm glass epoxy board mount. TA = 25C. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions TA = 25C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER Motor Supply Voltage Logic Supply Voltage Quiescent Power Supply Current Driver Circuit Power Supply Current Logic Supply Current (6) Gate Driver Circuit Power Supply Current Operating Power Supply Current Logic Supply Current (7) Gate Driver Circuit Power Supply Current (8) Low VDD Detection Voltage (9) Driver Output ON Resistance Source + Sink at IO = 0.7 A(10) RDS(ON) RDS(ON)2 - - 0.8 - 1.2 1.5 I IQ
M
Symbol
Min
Typ
Max
Unit
VM VDD
2.0 2.7
5.0 5.0
6.8 5.7
V V A
- - -
- - -
1.0 20 150 mA
QVDD I QVG IV I
DD
- - 1.5
- - 2.0
3.0 0.7 2.5 V
VG
VDD DET
VG = 9.5 V, VM = 5.0 V, TA = 25C(11) GATE DRIVE Gate Drive Circuit Power Supply Voltage CONTROL LOGIC Logic Input Voltage Logic Inputs (2.7 V < VDD < 5.7 V) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current
OE Pin Input Current Low
VG
12
13
13.5
V
VIN VIH VIL IIH IIL IIL-OE
0
-
VDD
- VDD x 0.3 1.0 - 100
V
VDD x 0.7 - - -1.0 -
- - - - 50
V V A A A
Notes 6. IQVDD includes the current to predriver circuit. 7. 8. 9. 10. 11. IV
DD includes the current to predriver circuit at fIN = 100 kHz.
At fIN = 20 kHz. Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When gate voltage VG is applied from an external source, VG = 7.5 V. The total H-Bridge ON resistance when VG is 13V. Increased RDS(ON) value as the result of a reduced VG value of 9.5 V.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions TA = 25C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted.
Characteristic INPUT Pulse Input Frequency Input Pulse Rise Time
(12)
Symbol
Min
Typ
Max
Unit
f IN tR tF
- - -
- - -
200 1.0
(13)
kHz s s
Input Pulse Fall Time (14) OUTPUT Propagation Delay Time (15) Turn-ON Time Turn-OFF Time Low-Voltage Detection Notes 12. 13. 14. 15. 16. Time(16)
1.0
(13)
s
t PLH t PHL
tV
DD DET
- - -
0.1 0.1 -
0.5 0.5 10 ms
Time is defined between 10% and 90%. That is, the input waveform slope must be steeper than this. Time is defined between 90% and 10%. Load of Output is 8.0 resistance. see figure 4 See figure 5.
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
IN1, IN2, OE
VDDDETon 50% VDD
2.5 V 50%
VDDDEToff
1.5 V
tPLH
OUTA, OUTB 90% 10%
tPHL
t
VDDDET 90%
t
VDDDET 0% (<1.0 A)
IM
Figure 4. tPLH, tPHL, and tPZH Timing Table 5. Truth Table
INPUT OE L L L L H IN1A IN2A L H L H X IN1B IN2B L L H H X
Figure 5. Low-Voltage Detection Timing Diagram
OUTPUT OUT1A OUT2A L H L Z Z OUT1B OUT2B L L H Z Z
H = High. L = Low. Z = High impedance. X = Don't care. OE pin is pulled up to VDD with internal resistance.
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 17533 is a monolithic dual H-Bridge ideal for portable electronic applications to control bipolar stepper motors and brush DC motors such as those found in camera len assemblies, camera shutters, optical disk drives, etc. The 17533 operates from 2.0 V to 6.8 V, with independent control of each H-Bridge via parallel MCU interface (3.0 Vand 5.0 V-compatible I/O). The device features built-in shootthrough current protection and undervoltage shutdown. The 17533 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). The MOSFETs comprising the output bridge have a total source + sink RDS(ON) 1.2 . The 17533 can simultaneously drive two brush DC motors or, as shown in the simplified application diagram on page 1, one bipolar stepper motor. The drivers are designed to be PWM'ed at frequencies up to 200 kHz.
FUNCTIONAL PIN DESCRIPTION LOGIC SUPPLY (VDD)
The VDD pin carries the logic supply voltage and current into the logic sections of the IC. VDD has an undervoltage threshold. If the supply voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input control pins.
OUTPUT A AND B OF H-BRIDGE CHANNEL 1 AND 2 (OUT1A, OUT1B, OUT2A, AND OUT2B)
These pins provide connection to the outputs of each of the internal H-Bridges (see Figure 2, 17533 Simplified Internal Block Diagram, page 2).
MOTOR DRIVE POWER SUPPLY (VM1 AND VM2)
The VM pins carry the main supply voltage and current into the power sections of the IC. This supply then becomes controlled and/or modulated by the IC as it delivers the power to the loads attached between the output pins. All VM pins must be connected together on the printed circuit board.
LOGIC INPUT CONTROL (IN1A, IN1B, IN2A, AND IN2B)
These logic input pins control each H-Bridge output (e.g., IN1A logic HIGH = OUT1A HIGH, etc.). However, if all inputs are taken HIGH, the outputs bridges are both tri-stated (refer to Table 5, Truth Table, page 7).
GATE DRIVER CIRCUIT VOLTAGE INPUT (VG)
The VG pin is the input pin for the gate drive voltage.
OUTPUT ENABLE (OE)
The OE pin is a LOW = TRUE enable input. When OE = HIGH, all H-Bridge outputs (OUT1A, OUT1B, OUT2A, and OUT2B) are tri-stated (high-impedance), regardless of logic inputs (IN1A, IN1B, IN2A, and IN2B) states.
POWER GROUND (PGND)
Power ground pins. They must be tied together on the PCB.
LOGIC GROUND (LGND)
Logic ground pin.
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TYPICAL APPLICATIONS INTRODUCTION
TYPICAL APPLICATIONS
INTRODUCTION
Figure 6 shows a typical application for the 17533. When applying the gate voltage to the VG pin from an external source, be sure to connect it via a resistor equal to, or greater than, RG = VG / 0.02 . Care must be taken to provide sufficient gate-source voltage for the high-side MOSFETs when VM >> VDD (e.g., VM = 5.0 V, VDD = 3.0 V), in order to ensure full enhancement of the high-side MOSFET channels.
5.0 V 17533
VG < 14 V RG > VG /0.02
VDD
VM
OUT1A
VG
RG 0.01 F
OUT1B
MCU
IN1A IN1B IN2A IN2B
OE
OUT2A
OUT2B
GND
Figure 6. 17533 Typical Application Diagram
CEMF SNUBBING TECHNIQUES
Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commuting currents in inductive loads. Typical practice is to provide snubbing of voltage transients by placing a zener or a capacitor at the supply pin (VM) (see Figure 7).
5.0 V 5.0 V 17533 VDD VM 5.0 V 5.0 V 17533 VDD VM
PCB LAYOUT
When designing the printed circuit board (PCB), connect sufficient capacitance between power supply and ground pins to ensure proper filtering from transients. For all highcurrent paths, use wide copper traces and shortest possible distances.
OUT
OUT
OUT OUT
OUT OUT
OUT GND
OUT GND
Figure 7. CEMF Snubbing Techniques
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PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search on the 98A number listed below.
EV (Pb-FREE) SUFFIX 16-LEAD VMFP PLASTIC PACKAGE 98ASA10614D ISSUE B
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REVISION HISTORY
REVISION HISTORY
REVISION 2.0 3.0
DATE 5/2006 7/2006
DESCRIPTION OF CHANGES
* * * * *
Converted to Freescale format Added Revision History page Updated to the prevailing form and style Corrected device isometric drawing on page 1 Added RoHS compliance
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MPC17533 Rev. 3.0 7/2006

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